1. Field of the Invention
The disclosed embodiments of the present invention relate to clock and data recovery circuit, and more particularly, to a multi-mode clock and data recovery circuit and a related method thereof.
2. Description of the Prior Art
In a communication system, a clock and data recovery circuit is employed in a receiver to sample the received signal (s) correctly. However, clock rates and data rates of systems dramatically rise along with the progress of the semiconductor process and the material technology. However, some systems, such as a passive optical network (PON) and a Gigabit-capable passive optical network (GPON), request that a receiver end should accomplish the clock and data recovery in a short time. The conventional solution to meet the aforesaid request is to employ a voltage controlled oscillator (VCO) in a phase-locked loop (PLL) for locking the frequency to provide a local clock in a receiver end, and further set a gated voltage controlled oscillator (GVCO) for locking the phase rapidly. Moreover, the GVCO is controlled by the same control voltage of the VCO, and locks the phase immediately after the frequency is locked.
Although two oscillators are controlled by the same control voltage, it is hard to guarantee that the semiconductor process or some other factors would not introduce frequency mismatches. That is to say, it may make the following clock and data recovery process more difficult, or induce a high bit error rate (BER) while an extreme condition, such as consecutive identical digits (CIDs), i.e., a serial data with a larger number of consecutive 0's or 1's, is encountered. Therefore, there is a need for an innovative design which can solve this troublesome issue.